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Introduction to Translation Lookaside Buffers

Understand how Translation Lookaside Buffers (TLBs) improve virtual memory efficiency by caching popular address translations. Learn the hardware support behind TLBs and their role in speeding up paging and address translation in operating systems.

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Using paging as the core mechanism to support virtual memory can lead to high performance overheads. By chopping the address space into small, fixed-sized units (i.e., pages), paging requires a large amount of mapping information. Because that mapping information is generally stored in physical memory, paging logically requires an extra memory lookup for each virtual address generated by the program. Going to memory for translation information before every instruction fetch or explicit load or store is prohibitively slow. And thus our problem:

THE CRUX: HOW TO SPEED UP ADDRESS TRANSLATION

How can we speed up ...