Mapping Table Size
Explore mapping table size issues in flash-based SSDs, focusing on page-level and block-level mapping. Learn how hybrid mapping and caching techniques balance memory costs and write performance, helping you grasp advanced SSD persistence design.
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The second cost of log-structuring is the potential for extremely large mapping tables, with one entry for each 4-KB page of the device. With a large 1-TB SSD, for example, a single 4-byte entry per 4-KB page results in 1 GB of memory needed the device, just for these mappings! Thus, this page-level FTL scheme is impractical.
Block-based mapping
One approach to reduce the costs of mapping is to only keep a pointer per block of the device, instead of per page, reducing the amount of mapping information by a factor of ...