Paging: Also Too Slow
Understand how paging affects system performance by requiring additional memory references for address translation. Learn about the process of translating virtual addresses to physical addresses using page tables and why this can slow systems down. This lesson highlights common problems with paging mechanisms and the need for optimized hardware and software designs.
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With page tables in memory, we already know that they might be too big. As it turns out, they can slow things down too.
Example
Take our simple instruction:
movl 21, %eax
Again, let’s just examine the explicit reference to address 21 and not worry about the instruction fetch. In this example, we’ll assume the hardware performs the translation for us. To fetch the desired data, the system must first translate the virtual address (21) into the correct physical address (117). Thus, before fetching the data from address 117, the system must first fetch the proper page table entry from the process’s page table, perform the translation, and then load the data from physical memory.
To do so, the hardware must know where the page table is for the currently-running process. Let’s assume for now that a single page-table base register contains the physical address of ...